An algorithmic approach for minimizing test power in VLSI circuits
نویسندگان
چکیده
منابع مشابه
Reordering Algorithm for Minimizing Test Power in VLSI Circuits
Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel method which aims at minimizing the total power consumption during testing. This is achieved by minimizing the switching activity in the circuit by reducing the Hamming Distance between successive test vectors. In this method ...
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ژورنال
عنوان ژورنال: IOP Conference Series: Materials Science and Engineering
سال: 2021
ISSN: 1757-8981,1757-899X
DOI: 10.1088/1757-899x/1059/1/012039